tag:blogger.com,1999:blog-40276689257573642682011-04-21T12:18:42.100-07:00Chip Verification, Chip Design Company, Chip Verification Services, Chip Verification Company, Firmware Development, Driver Development Framework, Video Driver Development, USB Driver Development, Board Support Package Development, Codec Optimization, Firmware Testing, Protocol Testing, Codec Testing, Device Driver Testing, India, USSibridge Technologies - Chip Design &amp; Chip Verification Companyhttp://www.blogger.com/profile/15658301750860445648noreply@blogger.comBlogger11100tag:blogger.com,1999:blog-4027668925757364268.post-33544815963082255272008-03-30T03:43:00.000-07:002008-03-30T04:37:28.644-07:00<a href="http://bp2.blogger.com/_v-6hrsmoto0/R-9wOPQREWI/AAAAAAAAABE/pbWLZ4VDp0I/s1600-h/logo_sibridge.jpg"><img id="BLOGGER_PHOTO_ID_5183485086041968994" style="FLOAT: left; MARGIN: 0px 10px 10px 0px; WIDTH: 435px; CURSOR: hand; HEIGHT: 123px" height="97" alt="" src="http://bp2.blogger.com/_v-6hrsmoto0/R-9wOPQREWI/AAAAAAAAABE/pbWLZ4VDp0I/s320/logo_sibridge.jpg" width="433" border="0" /></a><br /><div></div><div></div><div></div><div></div><div><strong><span style="font-size:130%;color:#3366ff;"></span></strong></div><div><strong><span style="font-size:130%;color:#3366ff;"></span></strong></div><div><strong><span style="font-size:130%;color:#3366ff;"></span></strong></div><div><strong><span style="font-size:130%;color:#3366ff;"></span></strong></div><div><strong><span style="font-size:130%;color:#3366ff;">Verification</span></strong></div><div><strong><span style="font-size:130%;color:#3366ff;"></span></strong></div><div><a href="http://bp1.blogger.com/_v-6hrsmoto0/R-9wJ_QREVI/AAAAAAAAAA8/R-qnnc75nMM/s1600-h/image2.jpg"><img id="BLOGGER_PHOTO_ID_5183485013027524946" style="FLOAT: left; MARGIN: 0px 10px 10px 0px; WIDTH: 39px; CURSOR: hand; HEIGHT: 41px" height="58" alt="" src="http://bp1.blogger.com/_v-6hrsmoto0/R-9wJ_QREVI/AAAAAAAAAA8/R-qnnc75nMM/s320/image2.jpg" width="76" border="0" /></a></div><div>Go to market </div><div>faster with </div><div>right- first-time-silicon </div><div><a href="http://www.sibridgetech.com/chip_verification.html">more...</a></div><div></div><div></div><div></div><div><span style="font-size:130%;color:#3366ff;"><strong></strong></span></div><div><span style="font-size:130%;color:#3366ff;"><strong><a href="http://bp3.blogger.com/_v-6hrsmoto0/R-9wEfQREUI/AAAAAAAAAA0/w-LBUFmBhws/s1600-h/vip_icon.jpg"><img id="BLOGGER_PHOTO_ID_5183484918538244418" style="FLOAT: left; MARGIN: 0px 10px 10px 0px; WIDTH: 39px; CURSOR: hand; HEIGHT: 43px" height="87" alt="" src="http://bp3.blogger.com/_v-6hrsmoto0/R-9wEfQREUI/AAAAAAAAAA0/w-LBUFmBhws/s320/vip_icon.jpg" width="92" border="0" /></a><a href="http://bp3.blogger.com/_v-6hrsmoto0/R-9wEfQREUI/AAAAAAAAAA0/w-LBUFmBhws/s1600-h/vip_icon.jpg"></a></strong></span></div><div>Expedite </div><div>your VIP </div><div>development </div><div><a href="http://www.sibridgetech.com/verificationip.html">more... </a></div><div></div><div></div><div></div><div><span style="font-size:130%;color:#3366ff;"><strong>Silicon Platform Software</strong></span></div><div><strong><span style="font-size:130%;color:#3366ff;"></span></strong></div><div><strong><span style="font-size:130%;color:#3366ff;"></span></strong></div><div></div><div><a href="http://bp0.blogger.com/_v-6hrsmoto0/R-9v9vQRETI/AAAAAAAAAAs/wR7ooOBER2c/s1600-h/firmware_icon.jpg"><img id="BLOGGER_PHOTO_ID_5183484802574127410" style="FLOAT: left; MARGIN: 0px 10px 10px 0px; WIDTH: 51px; CURSOR: hand; HEIGHT: 55px" height="77" alt="" src="http://bp0.blogger.com/_v-6hrsmoto0/R-9v9vQRETI/AAAAAAAAAAs/wR7ooOBER2c/s320/firmware_icon.jpg" width="86" border="0" /></a></div><div>Develop </div><div>firmware platform </div><div>for your SoC </div><div><a href="http://www.sibridgetech.com/firmwaredevelopment.html">more...</a></div><div></div><div></div><div></div><div></div><div></div><div><a href="http://bp0.blogger.com/_v-6hrsmoto0/R-9v1vQRESI/AAAAAAAAAAk/YtH-5UFWK2g/s1600-h/post_silicon_icon.jpg"><img id="BLOGGER_PHOTO_ID_5183484665135173922" style="FLOAT: left; MARGIN: 0px 10px 10px 0px; WIDTH: 48px; CURSOR: hand; HEIGHT: 52px" height="91" alt="" src="http://bp0.blogger.com/_v-6hrsmoto0/R-9v1vQRESI/AAAAAAAAAAk/YtH-5UFWK2g/s320/post_silicon_icon.jpg" width="88" border="0" /></a></div><div>Expedite your </div><div>SoC pre &amp; post–silicon </div><div>validation </div><div><a href="http://www.sibridgetech.com/siliconvalidation.html">more...</a></div><div><strong><span style="font-size:130%;color:#6633ff;"></span></strong></div><div><strong><span style="font-size:130%;color:#6633ff;"></span></strong></div><div><strong><span style="font-size:130%;color:#6633ff;">Chip Verification</span></strong></div><div><strong><span style="font-size:130%;color:#6633ff;"></span></strong></div><div></div><div><a href="http://bp0.blogger.com/_v-6hrsmoto0/R-9vrvQRERI/AAAAAAAAAAc/s3W6t5_dEAM/s1600-h/full_chip_dia.jpg"><img id="BLOGGER_PHOTO_ID_5183484493336482066" style="FLOAT: left; MARGIN: 0px 10px 10px 0px; WIDTH: 440px; CURSOR: hand; HEIGHT: 244px" height="244" alt="" src="http://bp0.blogger.com/_v-6hrsmoto0/R-9vrvQRERI/AAAAAAAAAAc/s3W6t5_dEAM/s320/full_chip_dia.jpg" width="385" border="0" /></a><span style="font-size:130%;"><strong><span style="color:#3366ff;"></span></strong></span></div><div><span style="font-size:130%;"><strong><span style="color:#3366ff;"></span></strong></span></div><div><span style="font-size:130%;"><strong><span style="color:#3366ff;"></span></strong></span></div><div><span style="font-size:130%;"><strong><span style="color:#3366ff;"></span></strong></span></div><div><span style="font-size:130%;"><strong><span style="color:#3366ff;"></span></strong></span></div><div><span style="font-size:130%;"><strong><span style="color:#3366ff;"></span></strong></span></div><div><span style="font-size:130%;"><strong><span style="color:#3366ff;"></span></strong></span></div><div><span style="font-size:130%;"><strong><span style="color:#3366ff;"></span></strong></span></div><div><span style="font-size:130%;"><strong><span style="color:#3366ff;"></span></strong></span></div><div><span style="font-size:130%;"><strong><span style="color:#3366ff;"></span></strong></span></div><div><span style="font-size:130%;"><strong><span style="color:#3366ff;"></span></strong></span></div><div><span style="font-size:130%;"><strong><span style="color:#3366ff;"></span></strong></span></div><div><span style="font-size:130%;"><strong><span style="color:#3366ff;"></span></strong></span></div><div><span style="font-size:130%;"><strong><span style="color:#3366ff;"></span></strong></span></div><div><span style="font-size:130%;"><strong><span style="color:#3366ff;"></span></strong></span></div><div><span style="font-size:130%;"><strong><span style="color:#3366ff;"></span></strong></span></div><div><span style="font-size:130%;"><strong><span style="color:#3366ff;"></span></strong></span></div><div><span style="font-size:130%;"><strong><span style="color:#3366ff;"></span></strong></span></div><div><span style="font-size:130%;"><strong><span style="color:#3366ff;"></span></strong></span></div><div><span style="font-size:130%;"><strong><span style="color:#3366ff;"></span></strong></span></div><div><span style="font-size:130%;"><strong><span style="color:#3366ff;"></span></strong></span></div><div><span style="font-size:130%;"><strong><span style="color:#3366ff;">Module to Chip Level verification</span></strong> </span></div><span style="font-size:130%;"><div align="justify"><br /></span></div><span style="font-size:78%;"><span style="font-family:verdana;font-size:85%;">Define verification strategy to ensure first time right silicon Define the verification environment for all levels of verification for maximum coverage Develop comprehensive test plans for module level and chip level to achieve zero bugs. Develop module and chip level coverage plan for maximum functions coverage with random testing. Develop highly efficient module and chip level verification environment with maximum reusability. Integration of industry standard VIP for maximum productivity gain. Development of module and chip level assertions. Develop efficient regression environment to reduce simulation time. Extensive experience in verification of SoCs with various interfaces like USB, PCI Express, Ethernet, PCI, etc and uPs like ARM, MIPS. Excellent experience in verification using SystemVerilog, Vera, e, SystemC/C++, Verilog, VHDL and mixed languages.</span> </span><div align="justify"></div><div align="justify"><strong><span style="font-size:130%;color:#3366ff;">Coverage driven verification</span></strong></div><div align="justify"></div><div align="justify"><span style="font-size:85%;">Develop verification strategy based on industry standard methodologies like VMM, RVM, AVM, eRM, UVM. Develop coverage plan for maximum functions coverage with random testing. Develop environment for coverage driven verification using SystemVerilog, Vera or e. Coverage development on legacy verification environment. Coverage plans for standard interfaces like USB, AHB, PCI Express. Assertion based verification</span></div><div></div><div><a href="http://bp2.blogger.com/_v-6hrsmoto0/R-9vmPQREQI/AAAAAAAAAAU/2_h3MepLKKY/s1600-h/full_chip_dia2.jpg"><img id="BLOGGER_PHOTO_ID_5183484398847201538" style="FLOAT: left; MARGIN: 0px 10px 10px 0px; WIDTH: 452px; CURSOR: hand; HEIGHT: 180px" height="180" alt="" src="http://bp2.blogger.com/_v-6hrsmoto0/R-9vmPQREQI/AAAAAAAAAAU/2_h3MepLKKY/s320/full_chip_dia2.jpg" width="367" border="0" /></a> </div><div></div><div></div><div></div><div></div><div></div><div></div><div></div><div><span style="font-size:130%;"><span style="color:#3366ff;"><strong></strong></span></span></div><div><span style="font-size:130%;"><span style="color:#3366ff;"><strong></strong></span></span></div><div><span style="font-size:130%;"><span style="color:#3366ff;"><strong></strong></span></span></div><div><span style="font-size:130%;"><span style="color:#3366ff;"><strong></strong></span></span></div><div><span style="font-size:130%;"><span style="color:#3366ff;"><strong></strong></span></span></div><div><span style="font-size:130%;"><span style="color:#3366ff;"><strong></strong></span></span></div><div><span style="font-size:130%;"><span style="color:#3366ff;"><strong></strong></span></span></div><div><span style="font-size:130%;"><span style="color:#3366ff;"><strong></strong></span></span></div><div><span style="font-size:130%;"><span style="color:#3366ff;"><strong>White box assertion development for design IPs.</strong></span> </span></div><div></div><div><span style="font-size:85%;">Experience in development of Assertion IPs for standard interfaces i.e. AHB, PCI, PCI Express, USB. Develop assertions using SVA, PSL and OVA.</span><br /></div><div><strong><span style="font-size:130%;"><span style="color:#3366ff;">Methodologies</span> </span></strong></div><div><strong><span style="font-size:130%;"></span></strong></div><div><a href="http://bp1.blogger.com/_v-6hrsmoto0/R-9vg_QREPI/AAAAAAAAAAM/h0LWhHFpLiM/s1600-h/full_chip_dia3.jpg"><img id="BLOGGER_PHOTO_ID_5183484308652888306" style="FLOAT: left; MARGIN: 0px 10px 10px 0px; WIDTH: 448px; CURSOR: hand; HEIGHT: 194px" height="194" alt="" src="http://bp1.blogger.com/_v-6hrsmoto0/R-9vg_QREPI/AAAAAAAAAAM/h0LWhHFpLiM/s320/full_chip_dia3.jpg" width="367" border="0" /></a><span style="font-size:85%;"></span></div><div><span style="font-size:85%;"></span></div><div><span style="font-size:85%;"></span></div><div><span style="font-size:85%;"></span></div><div><span style="font-size:85%;"></span></div><div><span style="font-size:85%;"></span></div><div><span style="font-size:85%;"></span></div><div><span style="font-size:85%;"></span></div><div><span style="font-size:85%;"></span></div><div><span style="font-size:85%;"></span></div><div><span style="font-size:85%;"></span></div><div><span style="font-size:85%;"></span></div><div><span style="font-size:85%;"></span></div><div><span style="font-size:85%;"></span></div><div><span style="font-size:85%;"></span></div><div><span style="font-size:85%;"></span></div><div><span style="font-size:85%;"></span></div><div><span style="font-size:85%;"></span></div><div><span style="font-size:85%;"></span></div><div><span style="font-size:85%;">Develop verification strategy based on coverage driven or directed test approach. Develop coverage verification strategy based on industry standard methodologies like VMM, RVM, AVM, eRM, UVM. Develop unified verification solution using different methodologies such as Verilog/VHDL, Coverage drive, assertion based. Implement assertion based verification methodology.</span> </div><div></div><div><strong><span style="color:#3366ff;">Press Releases</span></strong></div><div align="justify">Sibridge Technologies appoints semiconductor veteran as CEO to spearhead rapid growth. <a href="http://www.sibridgetech.com/semiconductor_veteran.html">more...</a></div><div align="justify">Sibridge launches Industry’s First OVM compliant GBE VIP in SystemVerilog. <a href="http://www.sibridgetech.com/ovm_compliant_gigabit_ethernet_press.html">more... </a><br /><br /><strong><span style="color:#3366ff;">Articles</span></strong> : Migrating Ethernet VIP to OVM Is a Cinch (Verification Horizons) <a href="http://www.sibridgetech.com/vip_to_ovm_articel.html">more...</a> </div><div align="justify"><span style="color:#ffffff;">Chip Design Company</span></div><div align="justify"></div><div align="center"><a href="http://www.sibridgetech.com/"><span style="color:#009900;"><strong>Home</strong></span></a><span style="color:#009900;"><strong> , </strong></span><a href="http://www.sibridgetech.com/vision.html"><span style="color:#009900;"><strong>About Us</strong></span></a><span style="color:#009900;"><strong> , </strong></span><a href="http://www.sibridgetech.com/contact.html"><span style="color:#009900;"><strong>Contact Us</strong></span></a><span style="color:#009900;"><strong> , </strong></span><a href="http://www.sibridgetech.com/sitemap.xml"><span style="color:#009900;"><strong>XML</strong></span></a><span style="color:#009900;"><strong>, </strong></span><a href="http://www.sibridgetech.com/sitemap.html"><span style="color:#009900;"><strong>Site Map</strong></span></a><span style="color:#009900;"><strong> , </strong></span><a href="http://www.sibridgetech.com/partners.html"><span style="color:#009900;"><strong>Partners</strong></span></a><span style="color:#009900;"><strong> , </strong></span><a href="http://www.sibridgetech.com/overview.html"><span style="color:#009900;"><strong>Overview</strong></span></a><span style="color:#009900;"><strong> , </strong></span><a href="http://www.sibridgetech.com/management_team.html"><span style="color:#009900;"><strong>Management Team</strong></span></a></div><div align="center"><span style="color:#ffffff;">Chip Design Services</span></div><div align="center"></div><div align="justify"></div><div align="justify"><strong><span style="color:#ff9900;">Verification : </span></strong><a href="http://www.sibridgetech.com/chip_verification.html">Chip Verification</a>, <a href="http://www.sibridgetech.com/verificationip.html">Verification IP Development</a>, <a href="http://www.sibridgetech.com/siliconvalidation.html">Migration Services, </a></div><div align="justify"></div><div align="justify"><strong><span style="color:#ff6600;">Silicon Platform Software : </span></strong><a href="http://www.sibridgetech.com/firmwaredevelopment.html">Firmware Development</a>, <a href="http://www.sibridgetech.com/siliconvalidation.html">Silication Validation</a></div><div align="justify"></div><div align="justify"></div><div align="justify">For Detail: <a href="http://www.sibridgetech.com/">http://www.sibridgetech.com/</a><br /><br /><br /><br /></div><div></div><div class="blogger-post-footer"><img width='1' height='1' src='https://blogger.googleusercontent.com/tracker/4027668925757364268-3354481596308225527?l=chip-design-company.blogspot.com' alt='' /></div>Sibridge Technologies - Chip Design &amp; Chip Verification Companyhttp://www.blogger.com/profile/15658301750860445648noreply@blogger.com0